Semiconductor device and method for manufacturing the same

ABSTRACT

A semiconductor device includes a semiconductor device comprising a semiconductor substrate, source/drain regions formed in the semiconductor substrate, a gate insulation film formed on the semiconductor substrate, a gate electrode formed on the gate insulation film between the source/drain regions, and a gate sidewall spacer formed on side surfaces of the gate electrode, wherein the gate sidewall spacer is composed of silicon oxide containing 0.1-30 atomic % of chlorine.

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is based upon and claims the benefit of priorityfrom the prior Japanese Patent Application No. 2002-003192, filed Jan.10, 2002; the entire contents of which are incorporated herein byreference.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates to a MOS transistor having animproved sidewall of a gate electrode and a method for manufacturing thesame.

[0004] 2. Description of the Related Art

[0005] As a structure of a semiconductor device is patterned finer,parasitic capacitance which is inevitably present in an elementstructure gives rise to a larger problem. For example, the parasiticcapacitance, which occurs between a gate electrode and a source/drainregion which provides a MOS transistor, reduces an operating speed ofthe transistor and has a larger effect as the elements are patternedfiner.

[0006]FIG. 7A shows part of a gate electrode structure of a conventionalMOS transistor. Provided on a semiconductor substrate 111 such assilicon is a gate insulation film 112 such as a silicon oxide film, onwhich a gate electrode 113 is formed. A source/drain region 116 isformed in the semiconductor substrate 111. Side and upper surfaces ofthe gate electrode 113 are covered with a gate protecting insulationfilm (Sidewall Oxide Layer) 114, and the side surface of the protectinginsulation film 114 is covered with a gate sidewall insulation film(Sidewall Spacer) 115 such as a silicon nitride film.

[0007] In the MOS transistor having such a configuration, the gateprotection film 114 and the gate sidewall insulation film 115 areinterposed as a dielectric between the gate electrode 113 and thesource/drain diffusion region 116 (including a wiring layer thereof), sothat there occurs unwanted parasitic capacitance.

[0008] Parasitic capacitance reduces the operating speed of thetransistor. Especially in a fine-patterned transistor having a gatelength of 0.2 μm or less, the parasitic capacitance reduces theoperating speed greatly.

[0009] Furthermore, a MOS transistor having an elevated source/drainconfiguration shown in FIG. 7B has an elevated source/drain layer 117which overlies the source/drain region 116 and is in contact with thegate sidewall spacer 115. This MOS transistor similarly suffers fromdrastic reduction in operating speed owing to large parasiticcapacitance between the gate electrode 113 and the elevated source/drainlayer 117 (including the wiring layer thereof) where the gate protectionfilm 114 and the gate sidewall spacer 115 are interposed therebetween.

[0010] Although silicon oxide has been used as a material of the gatesidewall spacer conventionally, silicon nitride with high dielectricconstant is used recently for a later-described reason. This has madethe problem of parasitic capacitance further serious.

[0011] FIGS. 8A-8D and FIGS. 9A-9C show a method for manufacturing a MOStransistor in a case where a conventional gate sidewall spacer is madeof silicon oxide.

[0012] As shown in FIG. 8A, after a gate oxide film 122 is formed on asilicon semiconductor substrate 121, a polysilicon film is deposited byChemical Vapor Deposition (CVD) and processed by Reactive Ion Etching(RIE) to form a gate electrode 123 thereof.

[0013] As shown in FIG. 8B, an exposed surface of the gate electrode 123is oxidized to form a gate protecting insulation film 124. Then, a part125 of a source/drain diffusion region is formed in the semiconductorsubstrate 121 by ion implantation.

[0014] As shown in FIG. 8C, a silicon oxide film is deposited by CVDover the substrate surface and then removed by RIE to form a gatesidewall spacer 126 thereof. In this case, the exposed surface of thesemiconductor substrate 121 is damaged by ions, so that a roughenedexposed surface is formed on the one part 125 of the source/drainregion.

[0015] As shown in FIG. 8D, a source/drain diffusion region 127 isformed in the semiconductor substrate 121 by ion implantation. In thiscase, since the surface of the semiconductor substrate 121 is roughened,variation in the shape of the diffusion regions occurs among theelements, which results in increased fluctuations in operatingcharacteristics thereof.

[0016] As shown in FIG. 9A, the oxide film is removed from the uppersurface of the gate electrode 123 using dilute hydrofluoric acid. Inthis case, the gate protection film 124 and the gate sidewall insulationfilm 126 are also removed partially. There are some cases where theinsulation film 126 of the sidewall spacer is left little by a type ofthe MOS transistor formed on the semiconductor substrate 121. Next, asshown in FIG. 9B, a cobalt layer 128 is deposited over the substratesurface by sputtering.

[0017] As shown in FIG. 9C, a cobalt silicide layer 129 is provided onthe gate electrode 123 and the source/drain region 127 by lamp heating.Thereafter, a non-reacted the cobalt layer is removed. In this case, inthe MOS transistor in which the insulation film of the gate sidewallspacer is not almost left, the gate electrode 123 and the source/drainregion 127 are electrically connected through the cobalt silicide layer129, thereby reducing the yield.

[0018] To eliminate such a problem in this case of using the siliconoxide as the gate sidewall spacer, a silicon nitride film has been usedas the gate sidewall spacer as shown in FIGS. 10A-10D and FIGS. 11A-11C.

[0019] After a gate oxide film 132 is formed on a semiconductorsubstrate 131 such as silicon, a gate electrode 133 such as apolysilicon film is formed thereon (FIG. 10A). Next, an exposed surfaceof the gate electrode 133 is oxidized to form a gate protectioninsulation film 134. Then, a part 135 of a source/drain diffusion regionis formed in the semiconductor substrate 131 by ion implantation (FIG.10B). A silicon nitride film is deposited over the substrate surface byCVD and then selectively removed by RIE to provide a gate sidewallinsulation spacer 136 on a side surface of the gate protection film 134.

[0020] According to the method, as shown in FIG. 10C, since the exposedface of the semiconductor substrate 131 can be prevented from beingroughened, the shape of the source/drain diffusion region 137 does notvary among elements as shown in FIG. 10D. Therefore, it is possible toreduce fluctuations in operating characteristics of the elements.

[0021] Furthermore, as shown in FIG. 11A, the gate sidewall spacer isnot removed during processing by use of dilute hydrofluoric acid, sothat as shown in FIG. 11C the gate electrode 133 and the source/drainregion 137 are not electrically connected, thereby preventing the yieldfrom being deteriorated.

[0022] According to this method, however, since the dielectric constantof the gate sidewall spacer is about twice as large as that of theconventional silicon oxide film, the parasitic capacitance is roughlydoubled, thus greatly reducing the operating speed of the element.

[0023] In this MOS transistor, a cobalt layer 138 is deposited over thesurface of the semiconductor substrate 131 by sputtering (FIG. 11B).Then, using the lamp heating, a cobalt silicide layer 139 is formed onthe gate electrode 133 and the source/drain region 137 (FIG. 11C). Anon-reacted cobalt layer is removed.

[0024] The above-mentioned problem occurs also in a case of forming aMOS transistor having an elevated source/drain structure shown in FIGS.12A-12D.

[0025] That is, FIGS. 12A-12D show a method for manufacturing a MOStransistor in a case of forming the gate sidewall spacer using thesilicon oxide.

[0026] As shown in FIG. 12A, after a gate oxide film 142 is formed on asemiconductor substrate 141 such as silicon, a polysilicon film and asilicon nitride film are deposited consecutively by CVD and processed byRIE to form a gate electrode 143 and a silicon nitride film 144sequentially.

[0027] As shown in FIG. 12B, after an exposed surface of the gateelectrode 143 is oxidized to form a gate protection film 145, a part 146of a source/drain diffusion region is formed in the silicon substrate byion implantation.

[0028] As shown in FIG. 12C, a silicon oxide film is deposited over thesurface of the semiconductor substrate 141 by CVD and then removed byRIE to form a gate sidewall spacer 147. In this case, the siliconsemiconductor substrate is exposed partially and subjected to impact byions, thereby providing a roughened surface thereon.

[0029] As shown in FIG. 12D, an elevated source/drain layer 148 isformed by epitaxial growth of silicon. In this case, a gap 150 called afacet is formed between the gate sidewall spacer 147 and the elevatedlayer 148.

[0030] A source/drain diffusion region 149 is formed in thesemiconductor substrate 141 by ion implantation. In this case, adiffusion region under the facet is formed deep, so that it is difficultto control a threshold value of the transistor owing to theshort-channel effect.

[0031] Therefore, a manufacturing method using a silicon nitride film isused as shown in FIGS. 13A-13D.

[0032] That is, as shown in FIG. 13A, after a gate oxide film 152 isformed on a semiconductor substrate 151 such as silicon, a polysiliconfilm and a silicon nitride film are deposited consecutively by CVD andprocessed by RIE to provide a gate electrode 153 and a silicon nitridefilm 154 sequentially.

[0033] As shown in FIG. 13B, after an exposed surface of the gateelectrode 153 is oxidized to form a gate protection film 155, a part 156of a source/drain diffusion region is formed in the silicon substrate151 by ion implantation.

[0034] As shown in FIG. 13C, a silicon nitride film is deposited overthe surface of the semiconductor substrate 151 by CVD and then removedfrom the flat portion by RIE to form a gate sidewall spacer 157.

[0035] According to the method, the surface of the semiconductorsubstrate in which the diffusion layer is formed is not roughened and,in addition, a gap called a facet is not formed between the gatesidewall spacer 157 and the elevated layer 158 as shown in FIG. 13D.Therefore, the source/drain diffusion region is formed just as designed,so that the threshold value of the transistors can be controlled easily.

[0036] According to this method, however, the dielectric constant of thegate sidewall spacer is about twice as large as that of a conventionalsilicon oxide film, so that the parasitic capacitance is also doubledapproximately, thus greatly reducing the operating speed of theelements.

[0037] As described above, to suppress variations in shape of thesource/drain diffusion region thereby to prevent an undesired failure ofshort-circuiting at the time of salicide formation, a silicon nitridefilm is used as at least part of the gate sidewall spacer of thefine-patterned transistor. Furthermore, in the transistor having theelevated source/drain structure, the sidewall spacer of silicon nitrideis used because of the facet formed at the time of the elevated layerformation. In addition, to prevent the semiconductor substrate frombeing dug at the time of forming the conductor plug connected to thesource/drain region, the transistor is covered with a so-called linerfilm of a silicon nitride film.

[0038] Such silicon nitride present around these transistors has higherdielectric constant than silicon oxide and so increases the parasiticcapacitance, thus greatly reducing the operating speed of thetransistors. Furthermore, trapped charge, distortions, hydrogen, etc.present in the silicon nitride film cause fluctuations incharacteristics of the transistors, thus reducing device reliabilities.

BRIEF SUMMARY OF THE INVENTION

[0039] According to a first aspect of the present invention, asemiconductor device comprises: a semiconductor substrate; source/drainregions formed in the semiconductor substrate; a gate insulation filmformed on the semiconductor substrate; a gate electrode formed on thegate insulation film between the source/drain regions; and a gatesidewall spacer formed on side surfaces of the gate electrode, whereinthe gate sidewall spacer is composed of silicon oxide containing 0.1-30atomic % of chlorine.

[0040] According to a second aspect of the present invention, asemiconductor device comprises: a semiconductor substrate; source/drainregions formed in the semiconductor substrate; a gate insulation filmformed on the semiconductor substrate; a gate electrode formed on thegate insulation film between the source/drain regions and covered with agate protecting insulation film; and a gate sidewall spacer formed onside surfaces of the gate electrode, wherein the gate sidewall spacer iscomposed of silicon oxide containing 0.1-30 atomic % of chlorine.

[0041] According to a third aspect of the present invention, a methodfor manufacturing a semiconductor device comprises forming source/drainregions in a semiconductor substrate; forming a gate insulation film onthe semiconductor substrate; forming a gate electrode on the gateinsulation film between the source/drain regions; forming an insulationfilm composed of a silicon nitride film containing chlorine on sidesurfaces of the gate electrode; and converting the silicon nitride filmby oxidation reaction processing into silicon oxide film containing0.1-30 atomic % of chlorine to provide a gate sidewall spacer.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

[0042]FIG. 1 is a plan view of a transistor according to a firstembodiment;

[0043]FIGS. 2A and 2B are cross-sectional views of the transistoraccording to the first embodiment and FIG. 2A is a cross-sectional viewtaken along line II-II of FIG. 1;

[0044]FIG. 3 is a graph for explaining a relationship between aconcentration of chlorine in a silicon oxide film and a rate of changein dielectric constant of the silicon oxide film;

[0045]FIGS. 4A to 4D are cross-sectional views for explaining atransistor manufacturing method according to a second embodiment;

[0046]FIGS. 5A to 5D are cross-sectional views for explaining thetransistor manufacturing method according to the second embodiment;

[0047]FIGS. 6A to 6D are cross-sectional views for explaining atransistor manufacturing method according to a third embodiment;

[0048]FIGS. 7A to 7B are cross-sectional views for explaining aconventional transistor manufacturing method;

[0049]FIGS. 8A to 8D are cross-sectional views for explaining theconventional transistor manufacturing method;

[0050]FIGS. 9A to 9C are cross-sectional views for explaining theconventional transistor manufacturing method;

[0051]FIGS. 10A to 10D are cross-sectional views for explaining theconventional transistor manufacturing method;

[0052]FIGS. 11A to 11C are cross-sectional views for explaining theconventional transistor manufacturing method;

[0053]FIGS. 12A to 12D are cross-sectional views for explaining theconventional transistor manufacturing method; and

[0054]FIGS. 13A to 13D are cross-sectional views for explaining theconventional transistor manufacturing method.

DETAILED DESCRIPTION OF THE INVENTION

[0055] The following will describe embodiments with reference todrawings.

[0056] First, a first embodiment is described with reference to FIGS.1-3.

[0057] As shown in FIG. 1 and FIGS. 2A-2B, on a semiconductor substrate11 such as silicon is formed a gate insulation film 12 of a siliconoxide film, on which a gate electrode 13 of polysilicon is provided.Source/drain regions 16 are provided in the semiconductor substrate 11.Side and upper surfaces of the gate electrode 13 are covered with a gateprotection insulation film (sidewall oxide layer) 14 of a silicon oxidefilm, in addition to which, the side surfaces covered with theprotection film 14 are further covered with a gate sidewall insulationfilm (sidewall spacer) 15. A gate length L is, for example, 0.2 μm orless. In a MOS transistor having such a structure, the parasiticcapacitance occurs between the gate electrode 13 and a source/draindiffusion region 16 (including a wiring layer).

[0058] Furthermore, in a semiconductor device having an elevatedsource/drain construction shown in FIG. 2B, provided on a semiconductorsubstrate is an elevated source/drain layer 17 made of, for example,monocrystal silicon which is on the source/drain region 16 and incontact with the gate sidewall spacer 15. The parasitic capacitanceoccurs between the gate electrode 13 and the elevated source/drain layer17 (including the wiring layer) where the gate protection film 14 andthe gate sidewall spacer 15 are interposed therebetween.

[0059] It is to be noted that the gate sidewall spacer 15 used in thesemiconductor device shown in FIGS. 2A-2B is composed of silicon oxidecontaining chlorine. For example, a silicon oxide film containingchlorine can be formed by plasma CVD using a silicon source gascontaining chlorine such as a dichlorosilane (SiH₂Cl₂) gas or atetrachlorosilane (SiCl₄) gas and an oxygen source gas such as adinitrogen monoxide (N₂O) gas or SiO₂ CVD with a chlorine (Cl₂) gas or ahydrogen chloride (HCl) gas as an additional source gas.

[0060]FIG. 3 is a graph for explaining dependency of a rate of change indielectric constant of a silicon oxide film containing chlorine on achlorine concentration. A vertical axis represents the rate of change inthe dielectric constant and a horizontal axis, a concentration ofchlorine (atomic %) in the silicon oxide film.

[0061]FIG. 3 shows a relationship between the rate of change in thedielectric constant of the silicon oxide film containing chlorine andthe chlorine concentration shown in Table 1. If the chlorineconcentration of the silicon oxide film containing chlorine is set to0.1 atomic % or higher, the dielectric constant of this silicon oxidefilm decreases essentially, thus enabling essentially reducing parasiticcapacitance between the gate electrode 13 and the source/drain diffusionregion 16 including the wiring layer (not shown) and that between thegate electrode 13 and the elevated source/drain layer 17 (including thewiring layer). It is to be noted that if the chlorine concentration isset to 1 atomic % or more, the parasitic capacitance can be reduced by5% or more, so that a remarkable advantage will be obtained especiallyin a fine-patterned transistor having a gate length of 0.2 μm or less.

[0062] In such a semiconductor device, the parasitic capacitance can bereduced, so that the thickness of the gate sidewall spacer can bedecreased, thus further promoting fine patterning of the elements.Furthermore, by containing chlorine in the silicon oxide film providingthe gate protection film which covers an exposed portion of the gateelectrode, the parasitic capacitance can be reduced between the gateelectrode and the source/drain region or the elevated source/drainlayer.

[0063] There is no upper limit in principle on the concentration ofchlorine contained in the silicon oxide film. If the chlorineconcentration increases, however, a hygroscopic property of siliconoxide becomes remarkable, thus rather increasing the dielectric constantin some cases depending on a method of forming elements. It is,therefore, preferable to set the concentration of chlorine in thesilicon oxide film to 30 atomic % or less essentially.

[0064] Furthermore, to reduce the dielectric constant, fluorine can beintroduced into the silicon oxide. Fluorine, however, has an adverseeffect such as promotion of diffusion of boron on a fine-patternedtransistor, so that it cannot suitably be used in place of chlorine andpreferably be used appropriately together with chlorine as occasiondemands. TABLE 1 Concentration of Rate of change in chlorine in silicondielectric constant oxide film containing of silicon oxide film chlorine(atom %) containing chlorine 0.01 1 0.1 0.99 1 0.95 5 0.87 13 0.76 160.71 30 0.59

[0065] The following will describe a second embodiment with reference toFIGS. 4A-4D and FIGS. 5A-5D.

[0066] As shown in FIG. 4A, on a surface of a semiconductor substrate 21such as silicon is formed a gate oxide film 22 by oxidation processing.Then, a polysilicon layer is deposited by CVD and processed by RIE toform a gate electrode 23. Thereafter, as shown in FIG. 4B, an exposedsurface of the gate electrode 23 is oxidized to form a gate protectionfilm 24. Then, a part 25 of a source/drain diffusion region is formed inthe semiconductor substrate 21 by ion implantation. As shown in FIG. 4C,a silicon nitride film is deposited over the substrate surface bylow-pressure CVD using a hexachlorodisilane (Si₂Cl₆) gas and an ammonia(NH₃) gas. The film forming condition is, for example, a temperature of400° C., a hexachlorodisilane gas flow rate of 1000 sccm, an ammonia gasflow rate of 10 sccm, and a pressure of 180 Pa. It has been confirmed bysecondary-ion mass spectroscopy that this silicon nitride film containsabout 10 atomic % of chlorine and hydrogen.

[0067] Thereafter, the silicon nitride film is selectively removed byRIE to provide a gate sidewall nitride film 26. In this case, by settingthe RIE rate of the gate oxide film 22 lower than that of the gatesidewall nitride film 26, the surface of the semiconductor substrate canbe prevented from being roughened.

[0068] As shown in FIG. 4D, a source/drain diffusion region 27 is formedin the semiconductor substrate 21 by ion implantation. In this case,since the surface of the semiconductor substrate is prevented from beingroughened, it is possible to suppress the shape of the diffusion regionfrom being varied from one another. This results in elimination offluctuations in operating characteristics of the elements.

[0069] Next, as shown in FIG. 5A, the gate oxide film is removed fromboth the upper surface of the gate electrode 23 and the surface of thesource/drain region 27 using dilute hydrofluoric acid. In this case,since the silicon nitride film is not almost etched, the gate sidewallspacer 26 remains in a desired shape on all of the elements.

[0070] As shown in FIG. 5B, a cobalt layer 28 is deposited over thesubstrate surface by sputtering. Then, as shown in FIG. 5C, a cobaltsilicide layer 29 is formed by the lamp heating on the upper surface ofthe gate electrode 23 and the surface of the source/drain region 27.

[0071] Thereafter, a non-reacted portion of the cobalt layer is removed.In this case, since the gate sidewall spacer 26 is formed already, thegate electrode 23 and the source/drain diffusion region 27 do notelectrically connected to each other, thereby essentially avoiding aproblem of a decrease in yield.

[0072] As shown in FIG. 5D, the gate sidewall spacer 26 of the nitridefilm can be annealed in a water vapor atmosphere to be converted into asilicon oxide film containing chlorine, which is provided as the gatesidewall insulation film 26′. The annealing condition is given by, forexample, a temperature of 150° C. and a pressure of 2 atmospheres. Ithas been confirmed by secondary-ion mass spectroscopy that this siliconoxide film contains of the order of 1 atomic % of chlorine and hydrogen.

[0073] Thereafter, an interlevel insulation film, a wiring layer, etc.are formed on the semiconductor substrate by a known method, thuscompleting the MOS transistor. In this case, since the nitride film ofthe gate sidewall spacer is converted into the silicon oxide filmalready, the parasitic capacitance is reduced between the gate electrode23 and the source/drain diffusion region 27 including the wiring layer,thus avoiding a decrease in operating speed of the elements.

[0074] In the above-described processing, the silicon nitride film isconverted into the silicon oxide film with annealing in the water vaporatmosphere. However, an oxidizing atmosphere of oxygen, ozone, etc., oran atmosphere of a mixture may be also used. A water vapor atmosphere,however, is suitable because the silicon nitride film is converted intothe silicon oxide film even at a low temperature. Furthermore, annealingmay be conducted at a pressure of 1 atmosphere or less but preferably beconducted at a pressure higher than 1 atmosphere.

[0075] The following will describe a third embodiment with reference toFIGS. 6A-6D.

[0076] In description of the present embodiment, steps are explained formanufacturing a transistor having an elevated source/drain structure.

[0077] First, as shown in FIG. 6A, on a semiconductor substrate 31 suchas silicon is formed a gate insulation film 32 such as a silicon oxidefilm. Then, a polysilicon layer and a silicon nitride film 34 whichserves as a mask for RIE processing are deposited by CVD consecutively,and the polysilicon is processed by RIE to form a gate electrode 33.Subsequently, an exposed surface of the gate electrode 33 is oxidized toform a gate protecting insulation film 35. Then, a part 36 of asource/drain diffusion region is formed in the semiconductor substrate31 by ion implantation.

[0078] As shown in FIG. 6B, a silicon nitride film is deposited over thesubstrate surface by low-pressure CVD using a hexachlorodisilane(Si₂Cl₆) gas and an ammonia (NH₃) gas. A film forming condition is givenby, for example, a temperature of 400° C., a hexachlorodisilane gas flowrate of 1000 sccm, an ammonia gas flow rate of 10 sccm, and a pressureof 180 Pa. Then, the silicon nitride film is removed by RIE to provide agate sidewall nitride film 37. In this case, by setting the RIE rate ofthe gate oxide film 32 lower than that of the gate sidewall nitride film37, the surface of the semiconductor substrate 31 is prevented frombeing roughened.

[0079] As shown in FIG. 6C, an elevated source/drain layer 38 is formedby epitaxial growth of silicon. The forming condition is given by, forexample, a temperature of 600° C., a dichlorosilane (SiH₂Cl₂) gas flowrate of 300 sccm, a germane (GeH₄) gas flow rate of 10 sccm, an hydrogenchloride gas flow rate of 100 sccm, a hydrogen gas flow rate of 1500sccm, and a pressure of 2 kPa. In this case, since the sidewall spacer37 is adjoined, a gap called the facet is not formed. The reason for useof the germane gas is to lower the forming temperature when the elevatedlayer 38 is produced. If the elevated layer is formed at a hightemperature, the silicon nitride film is densified and cannot be easilyconverted into the silicon oxide film later. A source/drain diffusionregion 39 is formed in the silicon substrate by ion implantation. Inthis case, the unwanted facet is prevented from being formed, so that itis possible to suppress the variation in the shape of the diffusionregions. Therefore, the threshold values of the transistors can becontrolled easily.

[0080] As shown in FIG. 6D, by annealing the sidewall nitride film 37 ina water vapor atmosphere, it is converted into the silicon oxide filmcontaining chlorine, thereby providing the gate sidewall spacer 37′. Theannealing condition is given by, for example, a temperature of 400° C.and a pressure of 1 atmosphere. It has been confirmed by secondary-ionmass spectroscopy that this silicon oxide film contains about 0.1 atom %of chlorine and hydrogen.

[0081] Thereafter, an interlevel insulation film, a wiring layer, etc.are provided on the semiconductor substrate by a known method, thuscompleting the MOS transistor.

[0082] In this case, since the gate sidewall insulation film isconverted into the silicon oxide film already, parasitic capacitance isreduced between the gate electrode 33 and the source/drain diffusionregion 38 including the wiring layer, thus avoiding a decrease inoperating speed of the elements.

[0083] Besides the above-mentioned embodiments, it is possible toconvert a silicon nitride film, which is present around a transistor,into a silicon oxide film after the element is completed. Once it isconverted into an oxide, it is possible to prevent a decrease inoperating speed of the transistor, reliability of the device, etc. owingto the silicon nitride film having a high dielectric constant.

[0084] Additional advantages and modifications will readily occur tothose skilled in the art. Therefore, the invention in its broaderaspects is not limited to the specific details and representativeembodiments shown and described herein. Accordingly, variousmodifications may be made without departing from the spirit or scope ofthe general invention concept as defined by the appended claims andtheir equivalents.

What is claimed is:
 1. A semiconductor device comprising: asemiconductor substrate; source/drain regions formed in thesemiconductor substrate; a gate insulation film formed on thesemiconductor substrate; a gate electrode formed on the gate insulationfilm between the source/drain regions; and a gate sidewall spacer formedon side surfaces of the gate electrode, wherein the gate sidewall spaceris composed of silicon oxide containing 0.1-30 atomic % of chlorine. 2.The semiconductor device according to claim 1, wherein the gateelectrode has a gate length of 0.2 μm or less.
 3. The semiconductordevice according to claim 1, wherein each of the source/drain regionshas an elevated source/drain structure.
 4. The semiconductor deviceaccording to claim 1, wherein a metal silicide layer is formed on anupper surface of the gate electrode and each of the source/drainregions.
 5. A semiconductor device comprising: a semiconductorsubstrate; source/drain regions formed in the semiconductor substrate; agate insulation film formed on the semiconductor substrate; a gateelectrode formed on the gate insulation film between the source/drainregions and covered with a gate protecting insulation film; and a gatesidewall spacer formed on side surfaces of the gate electrode, whereinthe gate sidewall spacer is composed of silicon oxide containing 0.1-30atomic % of chlorine.
 6. The semiconductor device according to claim 5,wherein the gate protecting insulation film is composed of silicon oxidecontaining 0.1-30 atomic % of chlorine.
 7. The semiconductor deviceaccording to claim 5, wherein the gate electrode has a gate length of0.2 μm or less.
 8. The semiconductor device according to claim 5,wherein each of the source/drain regions has an elevated source/drainstructure.
 9. The semiconductor device according to claim 5, wherein ametal silicide layer is formed on an upper surface of the gate electrodeand each of the source/drain regions.
 10. A method for manufacturing asemiconductor device, comprising: forming source/drain regions in asemiconductor substrate; forming a gate insulation film on thesemiconductor substrate; forming a gate electrode on the gate insulationfilm between the source/drain regions; forming an insulation filmcomposed of a silicon nitride film containing chlorine on side surfacesof the gate electrode; and converting the silicon nitride film byoxidation reaction processing into silicon oxide film containing 0.1-30atomic % of chlorine to provide a gate sidewall spacer.
 11. The methodaccording to claim 10, wherein the conversion into the silicon oxide isaccomplished by oxidizing reaction using water vapor as a main oxidationagent.
 12. The method according to claim 10, wherein the conversion intothe silicon oxide is accomplished by oxidizing reaction under a pressurein excess of the atmospheric pressure.